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X20C17 1 ?xicor, inc. 19 92, 1995 patents pending characteristics subject to change without notice 2015-2.4 3/28/96 t1/c2/d1 ns autostore? novram is a trademark of xicor, inc. high speed autostore? novram description the xicor X20C17 is a 2k x 8 novram featuring a high- speed static ram overlaid bit-for-bit with a nonvolatile electrically erasable prom (e 2 prom) and the autostore feature which automatically saves the ram contents to e 2 prom at power-down. the X20C17 is fabricated with advanced cmos floating gate technol- ogy to achieve high speed with low power and wide power-supply margin. the X20C17 features a compat- ible jedec approved byte-wide memory pinout for industry standard srams. the novram design allows data to be easily trans- ferred from ram to e 2 prom (store) and e 2 prom to ram (recall). the store operation is completed in 2.5ms or less. an automatic array recall operation reloads the contents of the e 2 prom into ram upon power-up. xicor novrams are designed for unlimited write operations to ram, either from the host or recalls from e 2 prom, and a minimum 1,000,000 store operations to the e 2 prom. data retention is specified to be greater than 100 years. features ? 24-pin standard sram dip pinout ? fast access time: 35ns, 45ns, 55ns ? high reliability endurance: 1,000,000 nonvolatile store operations retention: 100 years minimum ? autostore? novram automatically stores sram data into the e 2 prom array when v cc low threshold is detected e 2 prom data automatically recalled into ram upon power-up ? low power cmos standby: 250 m a ? infinite e 2 prom array recall, and ram read and write cycles 16k X20C17 2k x 8 bit pin configuration 2015 ill f02.1 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 i/o 0 i/o 1 i/o 2 v ss 1 v cc a 8 a 9 we oe a 10 ce i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 X20C17 2 3 4 5 6 7 8 9 10 11 12 22 23 24 21 20 19 18 17 16 15 14 13 plastic a pplication n ote available an56
X20C17 2 pin descriptions addresses (a 0 Ca 10 ) the address inputs select an 8-bit memory location during a read or write operation. chip enable ( ce ce ce ce ce ) the chip enable input must be low to enable all read/ write operations. when ce is high, power consumption is reduced. output enable ( oe oe oe oe oe ) the output enable input controls the data output buffers and is used to initiate read and recall operations. output enable low disables a store operation regardless of the state of ce , we . data in/data out (i/o 0 Ci/o 7 ) data is written to or read from the X20C17 through the i/o pins. the i/o pins are placed in the high impedance state when either ce or oe is high. write enable ( we we we we we ) the write enable input controls the writing of data to the static ram. functional diagram 2015 fhd f01.1 pin names symbol description a 0 Ca 10 address inputs i/o 0 Ci/o 7 data input/output we write enable ce chip enable oe output enable v cc +5v v ss ground 2015 pgm t01 v cc sense row select control logic column select & i/os eeprom array high speed 2k x 8 sram array ce oe we a 3 Ca 8 i/o 0 Ci/o 7 a 0 Ca 2 a 9 Ca 10 recall store
X20C17 3 device operation the ce , oe , and we inputs control the X20C17 opera- tion. the X20C17 byte-wide novram uses a 2-line control architecture to eliminate bus contention in a system environment. the i/o bus will be in a high impedance state when either oe or ce is high. ram operations ram read and write operations are performed as they would be with any static ram. a read operation requires ce and oe to be low. a write operation requires ce and we to be low. there is no limit to the number of read or write operations performed to the ram portion of the X20C17. memory transfer operations there are two memory transfer operations: a recall operation whereby the data stored in the e 2 prom array is transferred to the ram array; and a store operation which causes the entire contents of the ram array to be stored in the e 2 prom array. recall operations are performed automatically upon power-up. store operations are performed automatically upon power-down. the store operation take a maximum of 2.5ms. write protection the X20C17 supports two methods of protecting the nonvolatile data. if after power-up no ram write operations have occured, no autostore operation can be initiated. v cc sense C all functions are inhibited when v cc is 3v typical. symbol table the following symbol table provides a key to under- standing the conventions used in the device timing diagrams. the diagrams should be used in conjunction with the device timing specifications to determine actual device operation and performance, as well as device suitability for users application. waveform inputs outputs must be steady will be steady may change from low to high will change from low to high may change from high to low will change from high to low don? care: changes allowed changing: state not known n/a center line is high impedance
X20C17 4 d.c. operating characteristics (over recommended operating conditions unless otherwise specified.) limits symbol parameter min. max. units test conditions l cc1 v cc current (active) 100 ma we = v ih , ce = oe = v il address inputs = 0.4v/2.4v levels @ f = 20mhz, all i/os = open i cc2 (2) v cc current during 2.5 ma all i/os = open autostore i sb1 v cc standby current 10 ma all inputs = v ih , all i/os = open (ttl input) i sb2 v cc standby current 250 m a all inputs = v cc C 0.3v (cmos input) all i/os = open i li input leakage current 10 m av in = v ss to v cc i lo output leakage current 10 m av out = v ss to v cc , ce = v ih v il (1) input low voltage C1 0.8 v v ih (1) input high voltage 2 v cc + 1 v v ol output low voltage 0.4 v i ol = 4ma v oh output high voltage 2.4 v i oh = C4ma 2015 pgm t04.3 absolute maximum ratings* temperature under bias .................. C65 c to +135 c storage temperature ....................... C65 c to +150 c voltage on any pin with respect to v ss ....................................... C1v to +7v d.c. output current ........................................... 10ma lead temperature (soldering, 10 seconds) ...... 300 c *comment stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and the functional operation of the device at these or any conditions other than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. recommended operating conditions temperature min. max. commercial 0 c +70 c industrial C40 c +85 c military C55 c +125 c 2015 pgm t02.1 supply voltage limits X20C17 4.5v to 5.25v 2015 pgm t03.1 power-up timing symbol parameter max. units t pur (2) power-up to ram operation 100 m s t puw (2) power-up to nonvolatile operation 5 ms 2015 pgm t05 notes: (1) v il min. and v ih max. are for reference only and are not tested. (2) this parameter is periodically sampled and not 100% tested. capacitance t a = +25 c, f = 1mhz, v cc = 5v. symbol test max. units conditions c i/o (2) input/output capacitance 10 pf v i/o = 0v c in (2) input capacitance 6 pf v in = 0v 2015 pgm t06.2
X20C17 5 endurance and data retention parameter min. units endurance 100,000 data changes per bit store cycles 1,000,000 store cycles data retention 100 years 2015 pgm t07.1 equivalent a.c. load circuit a.c. conditions of test input pulse levels 0v to 3v input rise and fall times 5ns input and output timing levels 1.5v 2015 pgm t08.1 2015 fhd f04 mode selection ce ce ce ce ce we we we we we oe oe oe oe oe mode i/o power h x x not selected output high z standby l h l read ram output data active l l h write 1 ram input data high active l l h write 0 ram input data low active l l l not allowed output high z active l h h no operation output high z active 2015 pgm t09 5v 893 w 347 w output 30pf
X20C17 6 a.c. characteristics (over the recommended operating conditions unless otherwise specified) read cycle limits X20C17-35 X20C17-45 X20C17-55 symbol parameter min. max. min. max. min. max. units t rc read cycle time 35 45 55 ns t ce chip enable access time 35 45 55 ns t aa address access time 35 45 55 ns t oe output enable access time 20 25 30 ns t lz (3) chip enable to output in low z 0 0 0 ns t olz (3) output enable to output in low z 0 0 0 ns t hz (3) chip disable to output in high z 0 15 0 20 0 25 ns t ohz (3) output disable to output in high z 0 15 0 20 0 25 ns t oh output hold from address change 0 0 0 ns 2015 pgm t10 read cycle 2015 fhd f05 note: (3) t lz min., t hz , t olz min., and t ohz are periodically sampled and not 100% tested. t hz max. and t ohz max. are measured, with c l = 5pf, from the point when ce or oe return high (whichever occurs first) to the time when the outputs are no longer driven. t ce t rc address ce oe we data valid data valid t oe t lz t olz t oh t aa t hz t ohz data i/o t oe
X20C17 7 write cycle write cycle limits X20C17-35 X20C17-45 X20C17-55 symbol parameter min. max. min. max. min. max. units t wc write cycle time 35 45 55 ns t cw chip enable to end of write input 30 35 40 ns t as address setup time 0 0 0 ns t wp write pulse width 30 35 40 ns t wr write recovery time 0 0 0 ns t dw data setup to end of write 15 20 25 ns t dh data hold time 3 3 3 ns t oeh oe high hold time 0 0 0 ns t oes oe high setup time 0 0 0 ns t oz (4) output enable to output in high z 15 20 25 ns 2015 pgm t11 note: (4) t ow , t oz are periodically sampled and not 100% tested. 2015 fhd f06.1 t wc t cw t as t oz t wp t dw t dh t oeh t wr data valid address oe ce we data out data in
X20C17 8 autostore feature the autostore feature automatically saves the con- tents of the X20C17s static ram to the on-board bit-for- bit shadow e 2 prom at power-down. this circuitry in- sures that no data is lost during accidental power-downs or general system crashes, and is ideal for microproces- sor caching systems, embedded software systems, and general system back-up memory. autostore cycle limits X20C17 symbol parameter min. max. units t asto (5) autostore cycle time 2.5 ms v asth autostore threshold voltage 4.0 4.3 v v asend (5) autostore cycle end voltage 3.5 v 2015 pgm t15 1 2 3 4 5 v cc volts (v) time (ms) v asth v asend autostore cycle in progress t asto store time autostore cycle timing diagram and suggested autostore implementation circuit note: (5) t asto and v asend are periodically sampled and not 100% tested. the X20C17 automatically initiates a nonvolatile store cycle whenever vcc falls below the autostore thresh- old voltage (v asth ). v cc must remain above the autostore cycle end voltage (v asend ) for the dura- tion of the store cycle (t asto ). the detailed timing for this feature is illustrated in the autostore timing dia- gram, below. once the autostore cycle is initiated, all other device functions are inhibited. 2015 fhd f14 2015 ill f30.4 X20C17 v cc 22? cc v
X20C17 9 normalized i cc by temperature over the v cc range and frequency normalized i cc by temperature over frequency 1.4 1.2 0.8 0.4 0.6 0.2 1.0 0 2.0 i cc (normalized) frequency (mhz) 2015 fhd f33.2 -55 c +25 c +125 c 1.0 3.0 4.0 5.0 5.5 6.6 8.3 10.0 11.1 12.5 13.3 14.3 15.2 16.7 20.0 25.0 30.0 0.0 1.4 1.2 0.8 0.4 0.6 0.2 1.0 0 2.0 i cc (normalized) frequency (mhz) 2015 fhd f31.1 v cc = 5.5v v cc = 5.0v v cc = 4.5v 1.0 3.0 4.0 5.0 5.5 6.6 8.3 10.0 11.1 12.5 13.3 14.3 15.2 16.7 20.0 25.0 30.0 0.0
X20C17 10 packaging information 3926 fhd f03 note: 1. all dimensions in inches (in parentheses in millimeters) 2. package dimensions exclude molding flash 0.022 (0.56) 0.014 (0.36) 0.150 (3.81) 0.125 (3.18) 0.625 (15.87) 0.600 (15.24) 0.110 (2.79) 0.090 (2.29) 1.265 (32.13) 1.230 (31.24) 1.100 (27.94) ref. pin 1 index 0.162 (4.11) 0.140 (3.56) 0.030 (0.76) 0.015 (0.38) pin 1 seating plane 0.065 (1.65) 0.040 (1.02) 0.557 (14.15) 0.530 (13.46) 0.080 (2.03) 0.065 (1.65) 0 15 24-lead plastic dual in-line package type p typ. 0.010 (0.25)
X20C17 11 X20C17 x x -x ordering information access time C35 = 35ns C45 = 45ns C55 = 55ns temperature range blank = commercial = 0 c to +70 c i = industrial = C40 c to +85 c m = military = C55 c to +125 c package p = 24 lead plastic dip device limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemnification provisions appearing in its terms of sale only. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. xicor, inc. makes no warranty of merchantability or fitness tor any purpose. xicor, inc. reserves the right to discontinue production and change specifications and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no other circuits, patents, licenses are implied. us. patents xicor products are covered by one or more of the following u.s. patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976. foreign patents and additional patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. xicors products are not authorized for use as critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its satety or effectiveness.
X20C17 12 u.s. sales offices corporate office xicor inc. 1511 buckeye drive milpitas, ca 95035 phone: 408/432-8888 fax: 408/432-0640 e-mail: info@smtpgate.xicor.com northeast region xicor inc. 1344 main street waltham, ma 02154 phone: 617/899-5510 fax: 617/899-6808 e-mail: xicor-ne @smtpgate.xicor.com southeast region xicor inc. 100 e. sybelia ave. suite 355 maitland, fl 32751 phone: 407/740-8282 fax: 407/740-8602 e-mail: xicor-se @smtpgate.xicor.com southwest region xicor inc. 4100 newport place drive suite 710 newport beach, ca 92660 phone: 714/752-8700 fax: 714/752-8634 e-mail: xicor-sw @smtpgate.xicor.com northwest region xicor inc. 2700 augustine drive suite 219 santa clara, ca 95054 phone: 408/292-2011 fax: 408/980-9478 e-mail: xicor-nw @smtpgate.xicor.com mid-atlantic region xicor inc. 50 north street danbury, ct 06810 phone: 203/743-1701 fax: 203/794-9501 e-mail: xicor-ma @smtpgate.xicor.com north central region xicor inc. 810 south bartlett road suite 103 streamwood, il 60107 phone: 708/372-3200 fax: 708/372-3210 e-mail: xicor-nc @smtpgate.xicor.com south central region xicor inc. 11884 greenville ave. suite 102 dallas, tx 75243 phone: 214/669-2022 fax: 214/644-5835 e-mail: xicor-sc @smtpgate.xicor.com international sales offices singapore/malaysia/india xicor inc. 2700 augustine drive suite 219 santa clara, ca 95054 phone: 408/292-2011 fax: 408/980-9478 e-mail: xicor-nw @smtpgate.xicor.com korea xicor korea 27th fl., korea world trade ctr. 159, samsung-dong kangnam ku seoul 135-729 korea phone: (82) 2551.2750 fax: (82) 2551.2710 e-mail: xicor-ka @smtpgate.xicor.com ( ) = country code europe northern europe xicor ltd. grant thornton house witan way witney oxford ox8 6fe uk phone: (44) 1933.700544 fax: (44) 1933.700533 e-mail: xicor-uk @smtpgate.xicor.com central europe xicor gmbh technopark neukeferloh bretonischer ring 15 85630 grasbrunn bei muenchen germany phone: (49) 8946.10080 fax: (49) 8946.05472 e-mail: xicor-gm @smtpgate.xicor.com asia/pacific japan xicor japan k.k. suzuki building, 4th floor 1-6-8 shinjuku, shinjuku-ku tokyo 160, japan phone: (81) 3322.52004 fax: (81) 3322.52319 e-mail: xicor-jp @smtpgate.xicor.com mainland china taiwan/hong kong xicor inc. 4100 newport place drive suite 710 newport beach, ca 92660 phone: 714/752-8700 fax: 714/752-8634 e-mail: xicor-sw @smtpgate.xicor.com xicor, inc., marketing dept. 1511 buckeye drive, milpitas, california 95035-7493 tel 408/432-8888 fax 408/432-0640 rev. 4 3/96 stock# xx-x-xxxx xicor product information is available at: http://www.xicor.com

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